21 lines
405 B
Verilog
21 lines
405 B
Verilog
module bug;
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enum logic[1:0] {
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RST[2],
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IDLE,
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ACTIVE
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} state;
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initial begin
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state = RST0;
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#1 state = IDLE; // A non-blocking works, but IDLE is still a net
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#1 state = ACTIVE;
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#1 $display("PASSED");
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end
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other other(state == IDLE); // This is treating IDLE as a net
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endmodule
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module other(input logic val);
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always @(val) $display("%0t %b", $time, val);
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endmodule
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