32 lines
596 B
Verilog
32 lines
596 B
Verilog
module top;
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logic passed;
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logic [7:0] y;
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logic [7:0] yv;
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logic [39:0] a;
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logic [3:0][9:0] t;
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int idx;
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assign t = a;
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assign y = t[1][9-:8];
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assign yv = t[1][idx-:8];
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initial begin
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passed = 1'b1;
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idx = 9;
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a = {10'h3ff, 10'h2a5, 10'h000};
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#1;
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if (y != 8'ha9) begin
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$display("FAILED: expected 8'ha9 for constant select, got %h." , y);
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passed = 1'b0;
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end
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if (yv != 8'ha9) begin
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$display("FAILED: expected 8'ha9 for variable select, got %h." , yv);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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