29 lines
370 B
Verilog
29 lines
370 B
Verilog
package u_lib;
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class uvm_void;
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endclass
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class uvm_object extends uvm_void;
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task passed;
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$display("PASSED");
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endtask
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endclass
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endpackage
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package t1_pkg;
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import u_lib::*;
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class drvr extends uvm_object;
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endclass
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endpackage : t1_pkg
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module m;
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import t1_pkg::*;
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drvr obj;
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initial begin
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obj = new;
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obj.passed();
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end
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endmodule
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