31 lines
535 B
Verilog
31 lines
535 B
Verilog
module top;
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reg passed;
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reg a[];
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initial begin
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passed = 1'b1;
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a = new[3];
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a[0] = 1'b0;
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a[1] = 1'b1;
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if (a[0] !== 1'b0) begin
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$display("Failed a[0], expected 1'b0, got %b", a[0]);
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passed = 1'b0;
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end
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if (a[1] !== 1'b1) begin
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$display("Failed a[1], expected 1'b1, got %b", a[1]);
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passed = 1'b0;
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end
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if (a[2] !== 1'bx) begin
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$display("Failed a[2], expected 1'bx, got %b", a[2]);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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