18 lines
409 B
Verilog
18 lines
409 B
Verilog
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// To test the report of issue#451, run with this command line:
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//
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// iverilog -g2012 -Ptest.foo=4 br_gh451.v
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//
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module test #(parameter int foo = 8,
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parameter int bar = 2,
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parameter int math = bar * foo) (output reg [7:0] val);
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initial val = math;
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initial begin
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$display("foo=%0d", foo);
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$display("bar=%0d", bar);
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$display("math=%0d", math);
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end
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endmodule // test
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