25 lines
423 B
Verilog
25 lines
423 B
Verilog
module top;
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task tsk;
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$display("In task %m()");
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endtask
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function void fnc();
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$display("In function %m()");
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endfunction
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initial begin
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$display("In %m.initial");
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tsk();
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fnc();
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#10;
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$display("Done with simulation at %0d", $time);
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end
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final begin
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// tsk(); // This is from gh442 and is now an error
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fnc();
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$display("In %m.final");
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$display("PASSED");
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end
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endmodule
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