56 lines
1.3 KiB
Verilog
56 lines
1.3 KiB
Verilog
package t;
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class c;
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virtual function create (string name="");
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return null; // Error: logic returning a null
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endfunction
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endclass : c
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endpackage
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module m;
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import t::*;
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int idx, idx2;
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c carr [0:1][0:3];
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class c2;
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static c sval;
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c val;
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c arr [0:1];
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task check;
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if (sval == null) $display("Empty"); // Okay
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if (val == null) $display("Empty"); // Okay
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if (arr[0] == null) $display("Empty"); // Okay
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endtask
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endclass
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// An implicit logic return type is given a NULL
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function tmp();
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return null; // Error: logic returning a null
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endfunction
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c cls;
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logic val;
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initial begin
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idx = 0;
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idx2 = 0;
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if (cls == null) $display("Empty"); // Okay
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if (carr[0][0] == null) $display("Empty"); // Okay
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if (carr[idx][idx2] == null) $display("Empty"); // Okay
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if (0 == null) $display("Empty"); // Error: logic comp null
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val = 1|null; // Error: logic binop null
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val = 1<<null; // Error: logic binop null
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val = null<<1; // Error: logic binop null
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val = null==null; // Okay
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val = null<=1; // Error: null binop logic
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val = null<=cls; // Error: not supported
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val = !null; // Error: unary null
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val = null; // Error: null r-value
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val <= null; // Error: null r-value
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$display("FAILED");
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end
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endmodule
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