iverilog/ivtest/ivltests/br_gh418.v

24 lines
328 B
Verilog

module m;
reg [31:0] count = 0;
function void func1();
count++;
if (count < 10) func2();
endfunction
function void func2();
count++;
if (count < 10) func1();
endfunction
initial begin
func1();
if (count == 10)
$display("PASSED");
else
$display("FAILED");
end
endmodule