26 lines
337 B
Verilog
26 lines
337 B
Verilog
module test();
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typedef enum logic [8:0] { ILLEGAL, IA, IB } inst_t;
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inst_t ipb_inst;
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typedef struct packed {
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inst_t inst;
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logic iw;
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} ipb_data_t;
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ipb_data_t ipb_d;
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assign ipb_inst = ipb_d.inst;
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initial begin
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ipb_d.inst = IA;
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#1;
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if (ipb_inst === IA)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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