34 lines
695 B
Verilog
34 lines
695 B
Verilog
module test;
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string x[], y[], z[];
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string src[0:7];
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int i;
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initial begin
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src[0] = "a";
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src[1] = "b";
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src[2] = "c";
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src[3] = "d";
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src[4] = "e";
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src[5] = "f";
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src[6] = "g";
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src[7] = "h";
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x = new [4];
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for (i = 0; i < 4; i = i + 1) x[i] = src[i];
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y = x;
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z = new [4](x);
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for (i = 0; i < 4; i = i + 1) y[i] = src[3 - i];
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for (i = 0; i < 4; i = i + 1) z[i] = src[7 - i];
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// Expected output:
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// a b c d
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// d c b a
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// h g f e
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$display(x[0],,x[1],,x[2],,x[3]);
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$display(y[0],,y[1],,y[2],,y[3]);
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$display(z[0],,z[1],,z[2],,z[3]);
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end
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endmodule
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