23 lines
477 B
Verilog
23 lines
477 B
Verilog
module test;
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bit [7:0] i, x[], y[], z[];
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initial begin
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x = new [4];
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for (i = 0; i < 4; i = i + 1) x[i] = 1 + i;
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y = x;
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z = new [4](x);
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for (i = 0; i < 4; i = i + 1) y[i] = 4 - i;
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for (i = 0; i < 4; i = i + 1) z[i] = 8 - i;
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// Expected output:
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// 1 2 3 4
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// 4 3 2 1
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// 8 7 6 5
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$display(x[0],,x[1],,x[2],,x[3]);
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$display(y[0],,y[1],,y[2],,y[3]);
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$display(z[0],,z[1],,z[2],,z[3]);
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end
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endmodule
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