33 lines
565 B
Verilog
33 lines
565 B
Verilog
module tb();
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typedef enum logic [1:0] {
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IDLE = 0,
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RESET = 1,
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START = 2,
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WAITFOR = 3
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} stateType;
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stateType state;
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string workingString = "WORKING";
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initial begin
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$display("DIRECT ASSIGNED STRING is ", workingString);
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#10;
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state = IDLE;
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end
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string state_txt;
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always @* begin
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case(state)
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IDLE : state_txt = "IDLE";
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RESET : state_txt = "RST";
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START : state_txt = "STRT";
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WAITFOR : state_txt = "WAIT";
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endcase
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$display("Controller's new state is %s",state_txt);
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end
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endmodule
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