30 lines
774 B
Verilog
30 lines
774 B
Verilog
module a();
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// Need to add enumerations to packages.
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typedef enum logic[4:0] {
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EXC_A = 0,
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EXC_B = 1,
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EXC_C = 2
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} exc_code_t;
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// Need to search up the parent scope searching for the enum definition.
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function exc_code_t func1(bit inx);
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exc_code_t rVal;
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case(inx)
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1 : rVal = EXC_C;
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0: rVal = EXC_B;
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default: rVal = EXC_A;
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endcase
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return(rVal);
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endfunction
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exc_code_t exc_code;
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initial begin
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// Need to compare the base enumeration definition to check compatibility.
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exc_code = func1(1'b1);
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if(exc_code== EXC_C) begin
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$display("PASSED");
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$finish;
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end
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$display("FAILED");
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$finish;
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end
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endmodule
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