25 lines
473 B
Verilog
25 lines
473 B
Verilog
// Regression test for GitHub issue #33.
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module tb;
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reg [3:0] mem [0:15] [0:15];
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task cycle;
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input [3:0] a, b, c;
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reg [3:0] tmp;
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begin
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tmp = mem[a][b];
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mem[a][b] = c;
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$display("a=%d, b=%d, c=%d -> old=%d, new=%d", a, b, c, tmp, mem[a][b]);
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end
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endtask
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initial begin
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cycle( 7, 0, 1);
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cycle(15, 0, 2);
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cycle( 7, 0, 3);
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cycle(15, 0, 4);
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end
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endmodule
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