67 lines
992 B
Verilog
67 lines
992 B
Verilog
module dut(input EN, input DIR, inout A, inout B);
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assign A = EN && DIR == 0 ? B : 1'bz;
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assign B = EN && DIR == 1 ? A : 1'bz;
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specify
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(A => B) = (2);
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(B => A) = (3);
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(EN => A) = (4);
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(EN => B) = (4);
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endspecify
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endmodule
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module test();
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wire EN1;
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wire EN2;
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wire I1;
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wire I2;
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tri O;
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pulldown(O);
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dut dut1(EN1, 1'b1, I1, O);
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dut dut2(EN2, 1'b0, O, I2);
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reg failed = 0;
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initial begin
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$monitor($time,,EN1,,I1,,EN2,,I2,,O);
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force EN1 = 0;
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force EN2 = 0;
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#4;
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#0 if (O !== 0) failed = 1;
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force I1 = 1;
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force I2 = 1;
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#1;
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force EN1 = 1;
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#3;
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#0 if (O !== 0) failed = 1;
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#1;
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#0 if (O !== 1) failed = 1;
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force I1 = 0;
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#1;
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#0 if (O !== 1) failed = 1;
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#1;
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#0 if (O !== 0) failed = 1;
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force EN1 = 0;
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force EN2 = 1;
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#3;
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#0 if (O !== 0) failed = 1;
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#1;
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#0 if (O !== 1) failed = 1;
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force I2 = 0;
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#2;
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#0 if (O !== 1) failed = 1;
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#1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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