105 lines
2.5 KiB
Verilog
105 lines
2.5 KiB
Verilog
`timescale 1ns/1ns
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module hct74245(
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input dir,
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input nOE,
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inout [7:0] A,
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inout [7:0] B,
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output [7:0] C // Added to demonstrate that a straight dependency timing works correctly
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);
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// HCT typical @ 5v according to https://assets.nexperia.com/documents/data-sheet/74HC_HCT245.pdf
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specify
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(A *> C) = 100; // This delay works OK
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(A *> B) = 10; // The rest of these delays do not work
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(B *> A) = 10; // not respected
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(dir *> A) = 16;// not respected
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(dir *> B) = 16;// not respected
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(nOE *> A) = 16;// not respected
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(nOE *> B) = 16;// not respected
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endspecify
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assign A=nOE? 8'bzzzzzzzz : dir?8'bzzzzzzzz:B;
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assign B=nOE? 8'bzzzzzzzz : dir?A:8'bzzzzzzzz;
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assign C=A; // THIS IS DELAYED BY 100
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// HAVE TO USE THIS APPROACH TO MAKE TIMINGS WORK AT ALL
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// assign #16 A=nOE? 8'bzzzzzzzz :dir?8'bzzzzzzzz:B;
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// assign #16 B=nOE? 8'bzzzzzzzz :dir?A: 8'bzzzzzzzz;
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endmodule
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module tb();
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tri [7:0]A;
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tri [7:0]B;
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tri [7:0]C; // 'C' IS NOT PART OF ORIGINAL DESIGN - HOWEVER THIS TIMING IS RESPECTED COS THERE ARE NO CONDITIONALS IN THE ASSIGNMENT
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reg [7:0] Vb=8'b00000000;
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reg [7:0] Va=8'b11111111;
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reg dir;
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reg nOE;
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assign B=Vb;
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assign A=Va;
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hct74245 buf245(.A, .B, .dir, .nOE);
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integer timer;
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reg failed = 0;
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initial begin
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$display("disable output , set dir a->b");
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dir <= 1; // A->B
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nOE <= 1;
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Va=8'b11111111;
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Vb=8'bzzzzzzzz;
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#50 // time to settle
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// NOW throw outputs on and time how long it takes for expected output to appear.
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// It should take 16 to propagate from nOE -> B but the change is instantaneous
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$display("enable output - B will change immediately");
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timer=$time;
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nOE <= 0;
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wait(B === 8'b11111111);
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if ($time - timer < 16) begin
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$display("%6d", $time, " ERROR TOO QUICK - EXPECTED nOE->B = 16ns - BUT TOOK %-d", ($time - timer));
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failed = 1;
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end
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else
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$display("%6d", $time, " OK - TOOK %-d", ($time - timer));
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#50 // settle
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// Change data in - This should take 10 to propagate A->B but is instantaneous
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$display("change A - B will change immediately (but C is delayed as expected by 100)");
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Va=8'b00000000;
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timer=$time;
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nOE <= 0;
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wait(B === 8'b00000000);
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if ($time - timer < 10) begin
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$display("%6d", $time, " ERROR TOO QUICK - EXPECTED A->B = 10ns - BUT TOOK %-d", ($time - timer));
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failed = 1;
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end
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else
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$display("%6d", $time, " OK - TOOK %-d", ($time - timer));
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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