38 lines
689 B
Verilog
38 lines
689 B
Verilog
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typedef struct packed {
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logic b;
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} single_bit;
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typedef struct packed {
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single_bit b1;
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single_bit b2;
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} two_bits;
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module simple(input two_bits b2in,
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output two_bits b2out);
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assign b2out.b1.b = b2in.b1.b;
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endmodule // simple
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module main;
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two_bits src;
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wire two_bits dst;
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simple copy(src, dst);
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assign dst.b2.b = src.b2.b;
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initial begin
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src.b1.b = 1'b1;
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src.b2.b = 1'b0;
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#1 ; // Let values settle.
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$display("src=%b (s.b. 10), dst=%b (s.b. 10)", src, dst);
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if (src !== 2'b10 || dst !== 2'b10) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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