25 lines
407 B
Verilog
25 lines
407 B
Verilog
module counter(out, clk, reset);
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parameter WIDTH = 8;
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output [WIDTH-1 : 0] out;
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input clk, reset;
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reg [WIDTH-1 : 0] out;
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wire clk, reset;
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(* ivl_synthesis_on *)
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always @(posedge clk)
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out <= out + 1;
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always @(posedge reset)
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assign out = 0;
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always @(negedge reset)
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deassign out;
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(* ivl_synthesis_off *)
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initial $display("PASSED");
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endmodule // counter
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