23 lines
380 B
Verilog
23 lines
380 B
Verilog
module bug();
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reg d;
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reg [31:0] x;
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reg [31:0] y;
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reg [31:0] z;
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initial begin
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d = 1;
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x = 32'hffffffff << {d, 64'd0};
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y = 32'hffffffff >> {d, 64'd0};
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z = 32'hffffffff >>> {d, 64'd0};
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$display("%h", x);
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$display("%h", y);
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$display("%h", z);
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if (x === 32'd0 && y === 32'd0 && z === 32'd0)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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