28 lines
433 B
Verilog
28 lines
433 B
Verilog
module enumtestcase();
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typedef enum logic { STATE_A, STATE_B } t_STATE;
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t_STATE state;
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bit select;
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reg failed = 0;
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initial begin
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select = 0;
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state = select ? STATE_B : STATE_A;
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$display(state);
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if (state != STATE_A) failed = 1;
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select = 1;
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state = select ? STATE_B : STATE_A;
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$display(state);
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if (state != STATE_B) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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