25 lines
379 B
Verilog
25 lines
379 B
Verilog
// Regression test for GitHub issue #28 : Insufficient string escaping
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// when writing vvp script.
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module tb;
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wire [63:0] y;
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\test_str="hello" uut (y);
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initial begin
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#1 $display("%s", y);
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if (y === "hello")
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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module \test_str="hello" (output [63:0] \port="y" );
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assign \port="y" = "hello";
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endmodule
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