24 lines
435 B
Verilog
24 lines
435 B
Verilog
module test;
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reg [63:0] out;
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reg [5:0] in;
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integer i = 0;
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reg failed = 0;
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initial begin
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for (i = 0; i < 64; i = i + 1) begin
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in = i;
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out = 2 ** in;
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$display("%d: %b", i, out);
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if (out !== 64'd1 << i)
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failed = 1;
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end
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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