25 lines
412 B
Verilog
25 lines
412 B
Verilog
module Main();
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logic[2:0] a = 3'b111;
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logic signed[2:0] a_signed = 3'b111;
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logic[2:0] b = 0;
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logic[3:0] c0;
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logic[3:0] c1;
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initial begin
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c0 = 4'($signed(a)) + b;
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c1 = 4'(a_signed) + b;
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$display("c0: %b", c0);
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$display("c1: %b", c1);
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if (c0 === 4'b1111 && c1 === 4'b1111)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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