20 lines
306 B
Verilog
20 lines
306 B
Verilog
// Regression test for GitHub issue 19 : Icarus only using the lowest 32
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// bits of right shift operand (run-time test)
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module bug();
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reg a;
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reg y;
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initial begin
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a = 1;
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y = 1 >> {a, 64'b0};
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$display("%b", y);
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if (y === 1'b0)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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