25 lines
751 B
Verilog
25 lines
751 B
Verilog
module bug();
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reg [31:0] n1, d1, q1, m1;
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reg [63:0] n2, d2, q2, m2;
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initial begin
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n1 = 32'h8000_0000;
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d1 = 32'hFFFF_FFFF;
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q1 = $signed(n1) / $signed(d1);
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$display("32 bit quotient = 0x%08h;", q1);
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m1 = $signed(n1) % $signed(d1);
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$display("32 bit modulus = 0x%08h;", m1);
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n2 = 64'h8000_0000_0000_0000;
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d2 = 64'hFFFF_FFFF_FFFF_FFFF;
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q2 = $signed(n2) / $signed(d2);
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$display("64 bit quotient = 0x%016h;", q2);
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m2 = $signed(n2) % $signed(d2);
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$display("64 bit modulus = 0x%016h;", m2);
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if ((q1 === 32'h8000_0000) && (q2 === 64'h8000_0000_0000_0000)
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&& (m1 === 32'h0000_0000) && (m2 === 64'h0000_0000_0000_0000))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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