28 lines
783 B
Verilog
28 lines
783 B
Verilog
module test;
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real mema[];
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real memb[];
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reg failed = 0;
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initial begin
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mema = new[4] ('{1.5,2.5,3.5,4.5});
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$display("%f %f %f %f", mema[0], mema[1], mema[2], mema[3]);
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memb = new[4] (mema);
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$display("%f %f %f %f", memb[0], memb[1], memb[2], memb[3]);
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if (memb[0] != 1.5 || memb[1] != 2.5 || memb[2] != 3.5 || memb[3] != 4.5) failed = 1;
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memb = new[5] (memb);
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$display("%f %f %f %f %f", memb[0], memb[1], memb[2], memb[3], memb[4]);
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if (memb[0] != 1.5 || memb[1] != 2.5 || memb[2] != 3.5 || memb[3] != 4.5 || memb[4] != 0.0) failed = 1;
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memb = new[3] (memb);
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$display("%f %f %f", memb[0], memb[1], memb[2]);
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if (memb[0] != 1.5 || memb[1] != 2.5 || memb[2] != 3.5) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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