28 lines
809 B
Verilog
28 lines
809 B
Verilog
module test;
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int mema[];
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int memb[];
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reg failed = 0;
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initial begin
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mema = new[4] ('{8'd1,8'd2,8'd3,8'd4});
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$display("%x %x %x %x", mema[0], mema[1], mema[2], mema[3]);
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memb = new[4] (mema);
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$display("%x %x %x %x", memb[0], memb[1], memb[2], memb[3]);
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if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3 || memb[3] !== 8'd4) failed = 1;
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memb = new[5] (memb);
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$display("%x %x %x %x %x", memb[0], memb[1], memb[2], memb[3], memb[4]);
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if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3 || memb[3] !== 8'd4 || memb[4] !== 8'b0) failed = 1;
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memb = new[3] (memb);
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$display("%x %x %x", memb[0], memb[1], memb[2]);
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if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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