45 lines
941 B
Verilog
45 lines
941 B
Verilog
module bug();
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reg [0:1][0:15][0:7] array;
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reg failed = 0;
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integer i;
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reg [3:0] index;
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initial begin
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i = $bits(array);
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$display("width 0 = %0d", i);
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if (i !== 256) failed = 1;
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i = $bits(array[0]);
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$display("width 1 = %0d", i);
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if (i !== 128) failed = 1;
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i = $bits(array[0][0]);
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$display("width 2 = %0d", i);
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if (i !== 8) failed = 1;
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for (i = 0; i < 16; i++) begin
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index = i[3:0];
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array[0][index] = {4'd0, index};
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array[1][index] = {4'd1, index};
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end
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$display("%h", array);
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if (array !== 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f)
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failed = 1;
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for (i = 0; i < 16; i++) begin
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index = i[3:0];
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$display("%h : %h %h", index, array[0][index], array[1][index]);
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if (array[0][index] !== {4'd0, index}) failed = 1;
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if (array[1][index] !== {4'd1, index}) failed = 1;
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end
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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