36 lines
507 B
VHDL
36 lines
507 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity e is
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port (
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clk : in std_logic;
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rst : in std_logic;
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q : out std_logic);
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end e;
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architecture a of e is
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signal r : std_logic;
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function invert (
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i : std_logic)
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return std_logic is
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begin
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return not i;
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end invert;
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begin
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q <= r;
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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r <= '0';
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else
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r <= invert(r);
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end if;
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end if;
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end process;
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end a;
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