20 lines
314 B
Verilog
20 lines
314 B
Verilog
`begin_keywords "1364-2005"
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module top;
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localparam [8*8:0] expect = "0123456789";
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reg [8*8:0] str;
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reg passed;
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initial begin
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passed = $value$plusargs("string=%s", str);
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$display("%h", str);
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if (passed && (str == expect))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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`end_keywords
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