39 lines
713 B
Verilog
39 lines
713 B
Verilog
`begin_keywords "1364-2005"
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// Check that attributes are supported on all forms of
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// module port declaration.
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module m1(
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(* type=1, name="a" *) input wire a,
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(* type=1, name="b" *) inout wire b,
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(* type=1, name="c" *) output wire c,
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(* type=1, name="d" *) output reg d
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);
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endmodule
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module m2(a, b, c, d);
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(* type=2, name="a" *) input wire a;
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(* type=2, name="b" *) inout wire b;
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(* type=2, name="c" *) output wire c;
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(* type=2, name="d" *) output reg d;
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endmodule
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module m3(a, b, c, d);
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(* type=3 *) input a;
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(* type=3 *) inout b;
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(* type=3 *) output c;
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(* type=3 *) output d;
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(* name="a" *) wire a;
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(* name="b" *) wire b;
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(* name="c" *) wire c;
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(* name="d" *) reg d;
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endmodule
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`end_keywords
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