39 lines
597 B
Verilog
39 lines
597 B
Verilog
class aclass;
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reg [3:0] q[$];
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endclass
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module test;
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aclass a;
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reg [3:0] d;
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reg failed = 0;
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initial begin
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a = new;
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a.q.push_back(4'd1);
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a.q.push_back(4'd2);
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a.q.push_back(4'd3);
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a.q.push_back(4'd4);
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d = a.q.pop_front();
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$display("%h", d);
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if (d !== 4'd1) failed = 1;
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d = a.q.pop_front();
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$display("%h", d);
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if (d !== 4'd2) failed = 1;
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d = a.q.pop_front();
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$display("%h", d);
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if (d !== 4'd3) failed = 1;
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d = a.q.pop_front();
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$display("%h", d);
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if (d !== 4'd4) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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