30 lines
414 B
Verilog
30 lines
414 B
Verilog
timeunit 100ps / 10ps;
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function [63:0] delay(input dummy);
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begin
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$printtimescale(top);
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$printtimescale;
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delay = 5ns;
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end
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endfunction
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module top();
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timeunit 1ns / 1ps;
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reg [63:0] t1;
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reg [63:0] t2;
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initial begin
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$printtimescale;
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t1 = delay(0);
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t2 = 5ns;
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$display("%0d %0d", t1, t2);
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if ((t1 === 50) && (t2 === 5))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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