37 lines
479 B
Verilog
37 lines
479 B
Verilog
module loop();
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reg [3:0] a;
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reg [3:0] b;
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reg [3:0] c;
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reg [3:0] d;
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integer i;
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always @* begin
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for (i = 0; i < 4; i = i + 1) begin
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b[i] = a[i];
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$display("process 1 : %0d %b", i, b);
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end
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end
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always @* begin
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for (i = 0; i < 4; i = i + 1) begin
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d[i] = c[i];
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$display("process 2 : %0d %b", i, d);
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end
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end
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initial begin
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#0;
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a = 5;
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#0;
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c = 6;
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#0;
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if ((b === 5) && (c === 6))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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