59 lines
1.3 KiB
Verilog
59 lines
1.3 KiB
Verilog
/*
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* blocksyn1.v
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* This tests synthesis where statements in a block override previous
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* statements in a block and also uses other previous statements in the
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* block. Note in this example that the flag assignment is completely
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* overruled by the conditional that is directly after it.
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*/
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module main;
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reg [1:0] out;
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reg flag;
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reg [1:0] sel;
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(* ivl_synthesis_on, ivl_combinational *)
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always @*
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begin
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out = 2'b00;
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case (sel)
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2'b00: out = 2'b11;
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2'b01: out = 2'b10;
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2'b10: out = 2'b01;
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// out for sel==2'b11 should be inherited from previous statement
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endcase // case(sel)
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// This flag is completely overridden by the conditional, so
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// the synthesizer should drop it.
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flag = 1'b0;
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if (out == 2'b00)
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flag = 1'b1;
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else
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flag = 1'b0;
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end
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reg [2:0] idx;
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reg test;
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(* ivl_synthesis_off *)
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initial begin
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for (idx = 0 ; idx < 7 ; idx = idx + 1) begin
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sel = idx[1:0];
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#1 if (out !== ~sel) begin
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$display("FAILED -- sel=%b, out=%b, flag=%b", sel, out, flag);
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$finish;
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end
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test = (out == 2'b00)? 1'b1 : 1'b0;
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if (test !== flag) begin
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$display("FAILED -- test=%b, sel=%b, out=%b, flag=%b",
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test, sel, out, flag);
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$finish;
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end
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end // for (idx = 0 ; idx < 7 ; idx = idx + 1)
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$display("PASSED");
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end // initial begin
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endmodule // main
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