70 lines
1.2 KiB
Verilog
70 lines
1.2 KiB
Verilog
module main;
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wire [7:0] bus;
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reg [7:0] HiZ;
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assign bus = HiZ;
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reg E;
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reg D;
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reg CLK;
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BUFT drv (bus[0], D, E, CLK);
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bufif0 drv0 (bus[0], D, E);
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initial begin
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HiZ = 8'hzz;
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D = 1;
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E = 1;
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CLK = 0;
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#1 CLK = 1;
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#1 if (bus !== 8'bzzzzzzz1) begin
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$display("FAILED");
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$finish;
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end
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if (drv.D !== D) begin
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$display("FAILED (D)");
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$finish;
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end
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E = 0;
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#1 if (bus !== 8'bzzzzzzz1) begin
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$display("FAILED");
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$finish;
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end
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D = 0;
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CLK = 0;
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#1 CLK = 1;
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if (drv.D !== D) begin
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$display("FAILED (D)");
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$finish;
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end
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#1 D = 1;
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#1 if (bus !== 8'bzzzzzzz1) begin
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$display("FAILED");
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$finish;
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end
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if (drv.D !== D) begin
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$display("FAILED (D)");
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$finish;
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end
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$display("bus=%b, D=%b, drv.D=%b, E=%b, drv.save=%b", bus, D, drv.D, E, drv.save);
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$display("PASSED");
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end // initial begin
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endmodule // main
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module BUFT(inout wire TO, input wire D, input wire E, input wire CLK);
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reg save;
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assign TO = E? save : 2'bz;
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always @(posedge CLK)
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save <= D;
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endmodule // BUFT
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