164 lines
3.5 KiB
Verilog
164 lines
3.5 KiB
Verilog
// Note: when __ICARUS_UNSIZED__ is not defined, this test assumes integers
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// are 32 bits wide.
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module main();
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reg [34:0] my_reg;
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reg error;
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reg [34:0] ref_val;
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reg [34:0] ref_val2;
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reg [7:0] count;
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initial
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begin
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error = 0;
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// Create reference value that is bigger than 32 bits...
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ref_val = 0;
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ref_val[0] = 1;
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ref_val[34] = 1;
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$display("*:%d", ref_val);
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ref_val2 = 35'h7ffffffff;
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$display("*:%d", ref_val2);
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// Trivial test to see that small unsized integers still work.
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my_reg = 100;
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if (my_reg != 'h64)
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begin
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error = 1;
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$display("Error: expected 100");
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end
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my_reg = 17179869185;
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$display("1:%d", my_reg);
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`ifdef __ICARUS_UNSIZED__
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// Ordinary compilers will truncate unsized integer
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// constants to 32bits. Icarus Verilog is more generous.
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if (my_reg !== 35'h4_00000001) begin
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error = 1;
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$display("Error: expected 17179869185");
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end
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`else
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// Unsized integers bigger than 32 bits are truncated...
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// Value below has bit 34 and bit 0 set to '1'
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if (my_reg != 1)
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begin
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error = 1;
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$display("Error: expected 1");
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end
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`endif
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// Another unsized integer, but this time 'd specifier...
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my_reg = 'd17179869184;
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$display("2:%d", my_reg);
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`ifdef __ICARUS_UNSIZED__
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// Ordinary compilers will truncate unsized integer
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// constants to 32bits. Icarus Verilog is more generous.
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if (my_reg !== 35'h4_00000000) begin
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error = 1;
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$display("Error: expected 17179869184");
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end
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`else
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if (my_reg != 0)
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begin
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error = 1;
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$display("Error: expected 1");
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end
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`endif
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// This should finally work!
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my_reg = 35'sd17179869185;
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$display("3:%d", my_reg);
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if (my_reg != ref_val)
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begin
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error = 1;
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$display("Error: expected 17179869185");
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end
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// This should work too.
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my_reg = 35'd 17179869185;
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$display("4:%d", my_reg);
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if (my_reg != ref_val)
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begin
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error = 1;
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$display("Error: expected 17179869185");
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end
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// Overflow...
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my_reg = 35'd 34359738369;
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$display("5:%d", my_reg);
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if (my_reg != 1)
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begin
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error = 1;
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$display("Error: expected 1");
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end
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// Just no overflow
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my_reg = 35'd 34359738367;
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$display("6:%d", my_reg);
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if (my_reg != ref_val2)
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begin
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error = 1;
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$display("Error: expected 34359738367");
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end
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`ifdef __ICARUS_UNSIZED__
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// Since Icarus Verilog doesn't truncate constant values,
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// the whole idea of truncating then sign-extending the result
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// to go into the wide reg does not apply. So skip this
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// test.
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`else
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// Unsized integers bigger than 32 bits are truncated...
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// Here all the bits are set. Since there is no 'd prefix,
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// it will be sign extended later on.
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my_reg = 17179869183;
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$display("7:%d", my_reg);
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if (my_reg != ref_val2)
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begin
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error = 1;
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$display("Error: expected 34359738367");
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end
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`endif
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// Unsized integers bigger than 32 bits are truncated...
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// Here all the bits are set. Since there *IS* a 'd prefix
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// it will NOT be sign extended later on.
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my_reg = 'd17179869183;
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$display("8:%d", my_reg);
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`ifdef __ICARUS_UNSIZED__
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if (my_reg != 'd17179869183)
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begin
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error = 1;
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$display("Error: expected 'd17179869183");
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end
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`else
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if (my_reg != 'd4294967295)
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begin
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error = 1;
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$display("Error: expected 4294967295");
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end
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`endif
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if (error==1)
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begin
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$display("FAILED");
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end
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else
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begin
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$display("PASSED");
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end
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$finish;
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end
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endmodule
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