96 lines
2.0 KiB
Verilog
96 lines
2.0 KiB
Verilog
//
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// Copyright (c) 2002 Steven Wilson (steve@ka6s.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW: synth basic state machine form
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//
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//
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module sm ( clk,rst,st);
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input clk,rst;
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output [1:0] st;
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reg [1:0] st;
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always @(posedge clk or posedge rst)
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if (rst)
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st <= 2'b0;
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else
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case (st)
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2'b00: st <= 2'b01;
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2'b01: st <= 2'b11;
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2'b11: st <= 2'b10;
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2'b10: st <= 2'b00;
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endcase
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endmodule
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module test ;
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reg clk,rst;
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wire [1:0] st;
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sm u_sm ( clk,rst,st);
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always #5 clk = ~clk;
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initial
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begin
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// $dumpfile("test.vcd");
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// $dumpvars(0,test);
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clk = 0;
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rst = 1;
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@(posedge clk);
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#1 ;
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rst = 0;
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if(st !== 2'b00)
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begin
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$display("FAILED - SM didn't initialize");
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$finish;
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end
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@(posedge clk);
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#1 ;
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if(st !== 2'b01)
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begin
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$display("FAILED - SM didn't xsn to 01");
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$finish;
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end
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@(posedge clk);
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#1 ;
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if(st !== 2'b11)
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begin
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$display("FAILED - SM didn't xsn to 11");
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$finish;
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end
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@(posedge clk);
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#1 ;
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if(st !== 2'b10)
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begin
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$display("FAILED - SM didn't xsn to 10");
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$finish;
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end
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@(posedge clk);
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#1 ;
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if(st !== 2'b00)
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begin
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$display("FAILED - SM didn't xsn to 00");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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