62 lines
1.4 KiB
Verilog
62 lines
1.4 KiB
Verilog
//
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// Copyright (c) 2002 Steven Wilson (steve@ka6s.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW: Synth of basic expression assign with add
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//
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//
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module adder (q,a,b );
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input a,b;
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output [1:0] q;
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assign q = a + b;
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endmodule
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module test ;
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reg d;
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wire [1:0] q;
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adder u_add (.q(q),.a(d),.b(d));
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(* ivl_synthesis_off *)
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initial
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begin
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// $dumpfile("test.vcd");
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// $dumpvars(0,test);
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d = 0;
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# 1;
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if (q !== 2'b0)
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begin
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$display("FAILED - Q isn't 0 ");
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$finish;
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end
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#1 ;
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d = 1;
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# 1;
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if (q !== 2'b10)
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begin
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$display("FAILED - Q isn't 2 ");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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