42 lines
673 B
Verilog
42 lines
673 B
Verilog
// This test program is mostly about the parser parsing the attribute
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// attached to the main.dut.Q reg below.
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module main;
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reg CK;
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always begin
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#10 CK = 0;
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#10 CK = 1;
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end
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reg [3:0] D;
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wire [3:0] Q;
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test dut (.Q(Q), .D(D), .CK(CK));
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initial begin
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D = 0;
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@(posedge CK) #1 $display("Q=%b, D=%b", Q, D);
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if (Q !== D) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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module test (Q, D, CK);
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output [3:0] Q;
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input [3:0] D;
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input CK;
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(* REGISTER_DUPLICATION = "no" *)
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reg [3:0] Q;
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always @(posedge CK)
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Q <= D;
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endmodule // test
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