44 lines
927 B
Verilog
44 lines
927 B
Verilog
// Check that the assignment operator is supported for out-of-bounds indices on
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// real arrays. The write should be skipped, but side effects of the right-hand
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// side expression should still get evaluated.
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module test;
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real a[1:0];
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integer i;
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real r = 0;
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function real f;
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r += 0.125;
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return r;
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endfunction
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initial begin
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a[0] = 23.0;
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a[1] = 42.0;
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// Immediate out-of-bounds indices
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a[-1] += f();
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a[2] += f();
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a['hx] += f();
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// Variable out-of-bounds indices
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i = -1;
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a[i] += f();
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i = 2;
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a[i] += f();
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i = 'hx;
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a[i] += f();
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// Check that the in-bounds elements do not get affected by out-of-bounds
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// updates. Check that the left-hand side of the operator assignment gets
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// evaluated.
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if (a[0] == 23.0 && a[1] == 42.0 && r == 0.75) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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