26 lines
379 B
Verilog
26 lines
379 B
Verilog
module test();
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reg [3:0] count;
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reg carry;
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reg failed = 0;
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integer i;
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initial begin
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{carry, count} = 0;
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for (i = 0; i < 32; i += 1) begin
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$display("%b %b", carry, count);
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if (count !== i[3:0]) failed = 1;
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if (carry !== i[4]) failed = 1;
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{carry, count} += 1;
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end
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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