25 lines
546 B
Verilog
25 lines
546 B
Verilog
// Check that a assignment operator on an real array entry with an immediate
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// index works if it happes after a comparison that sets vvp flag 4 to 0.
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module test;
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real r[1:0];
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logic a = 1'b0;
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initial begin
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r[0] = 8.0;
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if (a == 0) begin
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// Make sure that this update happens, even though the compare above
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// cleared set vvp flag 4
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r[0] *= 2.0;
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end
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if (r[0] == 16.0) begin
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$display("PASSED");
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end else begin
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$display("FAILED. Expected %f, got %f", 16.0, r[0]);
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end
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end
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endmodule
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