23 lines
498 B
Verilog
23 lines
498 B
Verilog
// Check that a assignment operator on a dynamic part select of an vector works
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// if it happes after a comparison that sets vvp flag 4 to 0.
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module test;
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logic [7:0] a = 8'h0;
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initial begin
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if (a == 0) begin
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// Make sure that this update happens, even though the compare above
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// cleared set vvp flag 4
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a[a+:1] += 1;
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end
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if (a == 1) begin
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$display("PASSED");
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end else begin
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$display("FAILED. Expected 1, got %0d", a);
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end
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end
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endmodule
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