52 lines
1.4 KiB
Verilog
52 lines
1.4 KiB
Verilog
/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* Catch problems with non-zero lsb values in l-value expressions.
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*/
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module main;
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reg [7:1] a = 6'b111111;
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reg [7:1] b = 6'b000010;
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integer q;
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reg [7:1] x;
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reg PCLK = 1;
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always @(posedge PCLK)
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for (q=1; q<=7; q=q+1)
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x[q] <= #1 a[q] & b[q];
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always #5 PCLK = !PCLK;
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initial begin
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// $dumpfile("dump.vcd");
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// $dumpvars(0, main);
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#50 $display("done: x=%b", x);
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if (x !== 6'b000010)
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$display("FAILED -- x = %b", x);
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else
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$display("PASSED");
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$finish;
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end
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endmodule // main
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