54 lines
1.3 KiB
Verilog
54 lines
1.3 KiB
Verilog
/*
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* Copyright (c) 2000 Peter monta (pmonta@pacbell.net)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// Reworked by SDW to be self checking
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module main;
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reg [7:0] x;
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reg [7:0] y;
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reg [2:0] i; // Was a wire..
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reg error;
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initial begin
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#5;
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x[i] <= #1 0;
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y[i] = 0;
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end
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initial
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begin
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error = 0;
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#1;
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i = 1;
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#7;
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if(x[i] !== 1'b0)
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begin
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$display("FAILED - x[1] != 0");
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error = 1;
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end
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if(y[i] !== 1'b0)
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begin
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$display("FAILED - y[1] != 0");
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error = 1;
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end
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if(error === 0)
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$display("PASSED");
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end
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endmodule
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