77 lines
1.9 KiB
Verilog
77 lines
1.9 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate assign { ident0, ident1 } = expression ;
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module main ;
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wire a;
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wire [30:0] b;
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wire [14:0] c;
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reg [31:0] val;
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reg error;
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assign {b,a} = val; // full variable
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assign {c,a} = val[31:16]; // Top portion bit select
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initial
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begin
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error = 0;
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if(a != 1'bx)
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begin
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$display("FAILED - assign 3.2B assign ident = expr");
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error = 1;
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end
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if(b != 31'bx)
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begin
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$display("FAILED - assign 3.2B assign ident = expr");
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error = 1;
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end
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if(c != 14'bx)
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begin
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$display("FAILED - assign 3.2B assign ident = expr");
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error = 1;
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end
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#1 ;
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val = 32'h87654321;
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#1 ;
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if(a != 1'b1)
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begin
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$display("FAILED - 3.2A assign ident = expr");
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error = 1;
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end
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if(b != (32'h87654321) >> 1)
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begin
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$display("FAILED - 3.2A assign ident = expr");
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error = 1;
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end
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if(c != (16'h8765) >> 1)
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begin
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$display("FAILED - 3.2A assign ident = expr");
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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$finish ;
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end
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endmodule
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