21 lines
346 B
Verilog
21 lines
346 B
Verilog
module top;
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reg [7:0] array [1:0];
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reg \array[0] ;
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reg \array[1] ;
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integer idx;
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initial begin
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$dumpfile("work/dup.vcd");
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$dumpvars(0, array[0]);
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idx = 1;
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$dumpvars(0, array[idx]);
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$dumpvars(0, top);
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array[0] = 8'd0;
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#1
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array[0] = 8'd1;
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#1
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\array[0] = 1'b1;
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\array[1] = 1'b0;
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end
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endmodule
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