91 lines
2.3 KiB
Verilog
91 lines
2.3 KiB
Verilog
module top;
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reg pass = 1'b1;
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reg signed [7:0] arr [0:7];
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integer idx;
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reg signed [1:0] idx2;
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reg [7:0] res;
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real rarr [0:7];
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real rres;
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reg signed [2:0] a [0:3];
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wire signed [2:0] n [0:3];
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assign n[3] = 0;
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assign n[0] = -1;
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initial for (idx = 0; idx < 8 ; idx = idx + 1) rarr[idx] = idx+1.0;
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initial for (idx = 0; idx < 8 ; idx = idx + 1) arr[idx] = idx+1;
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initial begin
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#1;
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idx = 'bx;
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// Test %load/ar
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rres = rarr[idx];
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if (rres != 0.0) begin
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$display("Failed simple real array test, got %f.", rres);
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pass = 1'b0;
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end
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// Test %load/av
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res = arr[idx];
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if (res !== 8'bx) begin
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$display("Failed simple array vector test, got %b.", res);
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pass = 1'b0;
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end
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// Test %load/avp0
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res = arr[idx]+8'b1;
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if (res !== 8'bx) begin
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$display("Failed array vector plus constant test, got %b.", res);
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pass = 1'b0;
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end
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// Test %load/avp0/s
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res = arr[idx]+8'sb1;
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if (res !== 8'bx) begin
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$display("Failed array vector plus signed constant test, got %b.", res);
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pass = 1'b0;
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end
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// Test %load/avx.p with a 'bx array select.
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res = arr[idx][0];
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if (res !== 8'b0x) begin
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$display("Failed array vector bit select test 1, got %b.", res);
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pass = 1'b0;
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end
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// Test %load/avx.p with a 'bx bit select.
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res = arr[0][idx];
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if (res !== 8'b0x) begin
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$display("Failed array vector bit select test 2, got %b.", res);
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pass = 1'b0;
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end
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// Test %load/avx.p with a negative bit select.
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idx2 = -1;
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res = arr[0][idx2];
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if (res !== 8'b0x) begin
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$display("Failed array vector bit select test 3, got %b.", res);
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pass = 1'b0;
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end
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// This should be out of bounds and should be 'bx, but if this
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// is being loaded as an unsigned value it will return 1.
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idx2 = -1;
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a[3] = 0;
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a[0] = -1;
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res = arr[a[idx2]];
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if (res !== 8'bx) begin
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$display("Failed: reg array select driving array select, got %b", res);
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pass = 1'b0;
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end
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// The same here, but check a net array.
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res = arr[n[idx2]];
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if (res !== 8'bx) begin
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$display("Failed: wire array select driving array select, got %b", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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