32 lines
544 B
Verilog
32 lines
544 B
Verilog
module test;
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parameter width = 16;
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localparam count = 1<<width;
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reg [width-1:0] array[0: count-1];
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integer idx;
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initial begin
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for (idx = 0 ; idx < count ; idx = idx+1)
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array[idx] = idx;
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if (array[count/2] !== count/2) begin
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$display("FAILED");
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$finish;
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end
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if (array[0] !== 0) begin
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$display("FAILED");
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$finish;
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end
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for (idx = 0 ; idx < count ; idx = idx+1)
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if (array[idx] !== idx) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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